New Microchip Demonstrates Efficiency and Scalable Design

New Computer Chip Enhances Performance of Data Centre

A new computer chip which has been manufactured by Princeton University researchers tends to enhance the performance of data centres which is at the core of online services from email to social media. The data centres are basically giant warehouses which are overflowing with computer servers that enable cloud based services namely Gmail and Facebook and also store the amazingly huge content which is available through the internet.

 The computer chips which are at the cores of the largest server that tends to route as well as process information have a tendency to vary from the chips in smaller servers or the daily personal computers. Designing the chip precisely for massive computing systems, the researchers at Princeton inform that they can significantly upsurge the processing speed while lowering the needs of energy.

The chip architecture is said to be scalable wherein designs can be built which tends to go from a dozen processing units, known as cores, to many thousand. Moreover, the architecture permits thousands of chips to get linked together to an individual system comprising of millions of cores. Known as Piton, after the metal spikes which are driven by rock climbers into mountainsides to support during their ascent, it has been designed to scale.

Display How Servers Route Efficiently & Cheaply

David Wentzlaff, an assistant professor of electrical engineering and associated faculty in the Department of Computer Science at Princeton University commented that `with Piton, we really sat down and rethought computer architecture in order to build a chip specifically for data centres and the cloud.

The chip made, is among the largest chips ever built in academia and it displays how servers could route far more efficiently and cheaply’. The graduate student of Wentzlaff, Michael KcKeown, had provided a presentation regarding the Piton project at Hot Chips, s symposium on high performance chips in Cupertino, California.

The unveiling of the chip is said to be a conclusion on their year’s effort of Wentzlaff together with his students. Graduate student in Wentzlaff’s Princeton Parallel Group, Mohammad Shahrad commented that creating a physical piece of hardware in an academic setting could be rare and very special opportunity for computer architects.

The other researchers of Princeton who have been involved in the project since its commencement in 2013 comprise of Yaosheng Fu, Tri Nguyen, Yanqi Zhou, Jonathan Balkind, Alexey Lavrov, Matthew Matl, Xiaohua Liang and Samuel Payne, presently at NVIDIA.

Manufactured for Research Team by IBM

The Piton chip which been designed by the Princeton team had been manufactured for the research team by IBM. The main subsidy for the project had been provided from the National Science Foundation, the Defense Advanced Research Projects Agency and the Air Force Office of Scientific Research.

 The present variety of the Piton chip tends to measure six by six millimetres and the chip seems to have more than 460 million transistors. Each of them is small around 32 nanometres which are too small to be seen by anything but an electron microscope.

The bulk of these transistors are enclosed in 25 cores which is the independent processor for carrying out the instructions in a computer program. Several of the personal computer chips tend to have four or eight cores. Overall, more cores would mean faster processing times, till the software are capable of exploiting the available cores of the hardware in running operations in parallel. Hence the manufacturers of computer have resorted to multi-core chips to compress additional gains out of conventional approaches to computer hardware.

Prototype for Future Commercial Server System

Companies and academic institutions in recent years, had fashioned chips with several dozens of cores though Wentzlaff states that the readily scalable architecture of Piton tends to permit thousands of cores on an individual chip with half a billion cores in the data centre.

He commented that what they have with Piton is actually a prototype for the future commercial server system which tends to take advantage of a great amount of cores in speeding up the process. The design of the Piton chip is dedicated on exploiting unity among programs running all together on the same chip. One way of doing it is known as execution drafting which works just like the drafting in bicycle racing when the cyclist tends to conserve the energy behind a lead rider cutting through the air and creating a slipstream.

Multiple users at the data centre tend to run programs which depend on identical operations at the processor stage. The Piton chips’ cores has the capabilities of recognizing these instance and executes same instructions consecutively in order that the flow is continuous, just as a line of drafting cyclists. By doing so, it tends to increase the energy efficiency by around 20% in comparison to a standard core, according to the researchers.

Memory Traffic Shaper

A second modification incorporated in the Piton chip packages out when the opposing programs tend to access computer memory which is present off, the chip. Known as a memory traffic shaper, its operations is like a traffic cop at a busy intersection, considering the needs of each program and adapting memory request together with signalling them through suitably so that they do not congest the system.

 This method tends to yield around 18% jump in performance in comparison to conventional allocation. Moreover the Piton chip also tends to gain efficiency due to its management of memory stored on the chip which is known as the cache memory. This is faster in the computer and is utilised for accessing information, regularly.

In several designs, the cache memory is united across the entire chip’s cores though that approach could go wrong when multiple cores access and change the cache memory. However, Piton tends to evade this issue by assigning areas of the cache and precise cores to dedicated applications.

The researchers state that the system could increase the efficiency by 29% when it is applied to 1.024-core architecture and estimated that the savings could increase when the system is installed across millions of cores in a data centre. The researchers also informed that these developments could be implemented keeping the cost in line with the present manufacturing standards.

Intel Puts the Brakes on Moore’s Law

Intel – Slowing of Moore Law

A slowing of Moore’s Law which is a technological phenomenon that tends to play a role in mostmain advance in engineering and technology for years, has been signalled by chip maker Intel. Since 1970s, Intel had released chips which fit twice as many transistors in the similar space every two years with a goal of following an exponential curve called after Gordon Moor, one of the cofounders of the company.

Computer have become more powerful, compact and energy-efficient, due to continual shrinking and has helped in bringing about the smartphone, powerful Internet services together with breakthrough in fields like artificial intelligence and genetics. Moreover, Moore’s Law has become shorthand for notion that anything related to computing tends to get more accomplished over a period of time.

However, Intel had revealed in a regulatory filing last month that it intends slowing the pace where it launches new chip making technology. The breach between successive generations of chips with new, smaller transistor would widen and with the transistors in the latest chips of Intel, already as small as 14 nanometers, it is being more difficult to shrink them further in a way which would be cost effective for production.

Additional Performance Upgrades

The strategy of Intel to shift is not a surprise and it has already pushed back the debut of its first chips with 10 nanometer transistors from the end of this year to somewhere in 2017. However it is observed that the company has presently acknowledged that it was not a one-off and it cannot keep up the pace it used to keep.

This would mean Moore’s Law would be slowing down also. It does not mean that the devices would stop improving or ideas like driverless car would be stalled due to lack of processing power. Intel informs that it would deliver additional performance upgrades between generations of transistor technology with enhancement to the designing of the chips.

The Intel chips are basically immaterial to mobile devices, a market controlled by competitors who are usually behind in years with regards to terms of shrinking transistors and accepting new manufacturing technologies.

Intel – Switch Away From Silicon Transistors

It is also debatable that for several important new use incidents for computing like wearable devices or medical implants, chips have already been adequately powerful and consumption of power has become more important. However, raw computing power is still important and putting more of it behind machine learning procedure has been vital to the latest breakthroughs in artificial intelligence, for instance and Intel will probably deliver more bad news regarding the future of chips and Moore’s Law very soon.

The chief of manufacturing of the company, had mentioned in February that Intel desires to switch away from silicon transistors in around four years and stated before admitting that Intel does not have a successor lined up yet, that `the new technology would be basically different’.

 There have been two leading candidates, technologies known as spintronics and tunnelling transistors, though they may not provide large upsurges in computing powers. Both are far from being ready for use in making processors in huge volumes.

IBM Discloses Working Version of a Much Higher-Capacity Chip

IBM has taken the technology industry with surprise through its announcement of successfully developing working versions of ultradense computer chips. These chips are said to possess four times the capacity of today’s most powerful chips.

This announcement was essentially made on behalf of an international consortium led by IBM. IBM has invested $3 billion in an exclusive private public partnership in New York’s Hudson Valley with New York State, Samsung, GlobalFoundries and equipment vendors to manufacture advanced computer chips.

New Generation Of Chip In Development

It should be noted that each generation of chip is defined by the minimum size of fundamental components, which play role in switch current at nanosecond intervals. In modern times technology industry is actively working towards making a commercial transition from 14 nanometer to 10 nanometer manufacturing. Each generation helps in achieving 50 per cent reduction in the amount of area required for circuitry. IBM has affirmed its new chip which is still in research phase will be based on the shirking the area of semiconductor as much as possible by 2018.

IBM currently has working samples of chips with just seven nanometer transistors. It has been able to develop such sizes due to use of advanced silicon-gremanium instead of relying on pure silicon in key regions of chip. This material has made it possible to develop faster transistor switching with low power requirements, which is an added advantage. Given the smaller size of the transistors, it is highly possible to build microprocessors with not more than 20 billion transistors.

IBM Brings Focus Back On Itself As Revolutionary Chip Manufacturer

IBM has already shed a certain amount of its computer and semiconductor manufacturing capacity in the recent past. But this announcement shows that IBM is still interested in backing the technology manufacturing base with its efficient research facilities. Rather than being the horse power in building and providing chips to the companies it will act as a pioneer in unearthing advanced technological solutions for others. IBM will have to grapple with shift to use extreme ultraviolet (EUV) light for etching patterns on the chips at a resolution which approaches the diameter of an individual atom.

IBM will be licensing the technology to a variety of manufactures and most importantly, GlobalFoundries which is owned by the Emirate of Abu Dhabi will be making these chips for some big companies which includes, Qualcomm, Broadcom and others. It is yet to been whether semiconductor industry thinks on using silicon-gremanium as the best option or not.

IBM Refuses To Confirm Commercial Manufacturing

IBM has simply declined whether it will begin commercial manufacturing of this technology or not. Another ambitious company named Taiwan Semiconductor Manufacturing Company had given green lights to its plans to begin production of seven nanometer chips in 2017.

Given the precision required for using EUV light to keep the high capacity usage of chips optimum might be a concern in the commercial manufacturing operations. The goal of IBM here is to create next generation circuits, which offer higher capacity with reduced area, and most probably with current advancements and right amount of further research this technology will be introduced next year.